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a ad7851 functional block diagram ain (+) ain (? c ref1 c ref2 cal av dd agnd agnd dv dd dgnd amode clkin sleep convst busy sync sm1 sm2 din dout sclk polarity charge redistribution dac comp 4.096v reference ad7851 buf t/h sar + adc control calibration memory and controller serial interface/control register ref in / ref out 14-bit 333 ksps serial a/d converter features single 5 v supply 333 ksps throughput rate/ 2 lsb dnl? grade 285 ksps throughput rate/ 1 lsb dnl? grade a and k grades guaranteed to 125 c/238 ksps throughput rate pseudo-differential input with two input ranges system and self-calibration with autocalibration on power-up read/write capability of calibration data low power: 60 mw typ power-down mode: 5 w typ power consumption flexible serial interface: 8051/spi /qspi/ p compatible 24-lead pdip, soic, and ssop packages applications digital signal processing speech recognition and synthesis spectrum analysis dsp servo control instrumentation and control systems high speed modems automotive general description the ad7851 is a high speed, 14-bit adc that operates from a single 5 v power supply. the adc powers up with a set of default conditions at which time it can be operated as a read-only adc. the adc contains self-calibration and system calibration options to ensure accurate operation over time and temperature and has a number of power-down options for low power applications. the ad7851 is capable of a 333 khz throughput rate. the input track-and-hold acquires a signal in 0.33 s and features a pseudo-differential sampling scheme. the ad7851 has the added advantage of two input voltage ranges (0 v to v ref and ? ref /2 to +v ref /2 centered about v ref /2). input signal range is to v dd and the part is capable of converting full power signals to 20 mhz. cmos construction ensures low power dissipation (60 mw typ) with power-down mode (5 w typ). the part is available in a 24-lead, 0.3 inch-wide pdip, a 24-lead soic, and a 24-lead ssop package. product highlights 1. single 5 v supply. 2. operates with reference voltages from 4 v to v dd . 3. analog input ranges from 0 v to v dd . 4. system and self-calibration including power-down mode. 5. versatile serial i/o port. rev. b one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners.
ad7851 e2e rev. b table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 product highlights . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 5 typical timing diagrams . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . 7 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin function descriptions . . . . . . . . . . . . . . . . . . 9 ad7851 on-chip registers . . . . . . . . . . . . . . . . . . . . 10 addressing the on-chip registers . . . . . . . . . . . . . . . . . . 10 writing/reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 calibration registers . . . . . . . . . . . . . . . . . . . . . . 13 addressing the calibration registers . . . . . . . . . . . . . . . . 13 writing to/reading from the calibration registers . . . . . . 13 adjusting the offset calibration register . . . . . . . . . . . . . 14 adjusting the gain calibration registers . . . . . . . . . . . . . 14 circuit information . . . . . . . . . . . . . . . . . . . . . . . . 15 converter details . . . . . . . . . . . . . . . . . . . . . . . . . . 15 typical connection diagram . . . . . . . . . . . . . . 15 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 dc/ac applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 input ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reference section . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ad7851 performance curves . . . . . . . . . . . . . . . . 18 power-down options . . . . . . . . . . . . . . . . . . . . . . . . 19 power-up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 using an external reference . . . . . . . . . . . . . . . . . . . . . . 20 using the internal (on-chip) reference . . . . . . . . . . . . . 20 power vs. throughput rate . . . . . . . . . . . . . . . . 20 calibration section . . . . . . . . . . . . . . . . . . . . . . . . 21 calibration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 automatic calibration on power-on . . . . . . . . . . . . . . . . 21 self-calibration description . . . . . . . . . . . . . . . . . . . . . . . 21 self-calibration timing . . . . . . . . . . . . . . . . . . . . . . . . . . 22 system calibration description . . . . . . . . . . . . . . . . . . . . 22 system gain and offset interaction . . . . . . . . . . . . . . . . . 23 system calibration timing . . . . . . . . . . . . . . . . . . . . . . . 23 serial interface summary . . . . . . . . . . . . . . . . . . 24 resetting the serial interface . . . . . . . . . . . . . . . . . . . . . . 24 detailed timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mode 1 (2-wire 8051 interface) . . . . . . . . . . . . . . . . . . . 25 mode 2 (3-wire spi/qspi interface mode) . . . . . . . . . . . 26 mode 3 (qspi interface mode) . . . . . . . . . . . . . . . . . . . . 26 mode 4 and 5 (self-clocking modes) . . . . . . . . . . . . . . . 27 configuring the ad7851 . . . . . . . . . . . . . . . . . . . . . 28 ad7851 as a read-only adc . . . . . . . . . . . . . . . . . . . . . 28 writing to the ad7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 29 interface modes 2 and 3 configuration . . . . . . . . . . . . . . 29 interface mode 1 configuration . . . . . . . . . . . . . . . . . . . . 30 interface modes 4 and 5 configuration . . . . . . . . . . . . . . 30 microprocessor interfacing . . . . . . . . . . . . . . . 31 ad7851 to 8xc51/pic17c42 interface . . . . . . . . . . . . . . . 31 ad7851 to 68hc11/16/l11/pic16c42 interface . . . . . . . . 31 ad7851 to adsp-21xx interface . . . . . . . . . . . . . . . . . . . . 32 ad7851 to dsp56000/1/2/l002 interface . . . . . . . . . . . . . 32 ad7851 to tms320c20/25/5x/lc5x interface . . . . . . . . . 32 applications hints . . . . . . . . . . . . . . . . . . . . . . . . . . 33 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 evaluating the ad7851 performance . . . . . . . . . . . . . . . . 33 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 34 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
e3e rev. b ad7851 a grade: f clkin = 7 mhz (e40 c to +85 c), f sample = 333 khz; k grade: f clkin = 6 mhz (0 c to 85 c), f sample = 285 khz; a and k grade: f clkin = 5 mhz (to 125 c), f sample = 238 khz; (av dd = dv dd = 5.0 v 5%, ref in /ref out = 4.096 v external reference; s leep l p pee s s s s sple s sple ps sple s sple sple p ls ls e ls pse ls se ls e ls lp e e e e e e e l eeeepp e e e lps l l lps se l l s sl s s ese l l spes
ad7851 e4e rev. b parameter version a 1 version k 1 unit test conditions/comments power performance av dd, dv dd 4.75/5.25 4.75/5.25 v min/max i dd normal mode 4 17 17 ma max av dd = dv dd = 4.75 v to 5.25 v. typically 12 ma. sleep mode 5 with external clock on 20 20 a typ full power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 0. 600 600 a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1. with external clock off 10 10 a max typically 1 a. full power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 0. 300 300 a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1. normal mode power dissipation 89.25 89.25 mw max v dd = 5.25 v: typically 63 mw; sleep v s p e c o v v sleep v e c o v v t sleep v syste calaton o c s v e v e v a o v s c c s v e v e v a s v s c notes t a v c c v c c s 3 sn a n convst sleep cal sync v n a an cln n a n convst sleep cal sync v n a an t a n an an v e an an v e v e t c s
e5e rev. b ad7851 descriptions that refer to sclk (rising) or sclk (falling) edges are with the polarity pin high. for the polarity pin low, then the opposite edge of sclk will apply. limit at t min , t max parameter (a, k versions) unit description f clkin 2 500 khz min master clock frequency 7 mhz max f sclk 3 10 mhz max interface modes 1, 2, 3 (external serial clock) f clk in mhz max interface modes 4, 5 (internal serial clock) t 1 4 100 ns min convst p convst sy p convet 3 c t cln 3 scl sync scl s t n scl scl sync scl s t c scl scl sync scl s t o 3 sync ot ts a 3 sync n ts a t scl 3 s t scl v scl h t scl scl h p scl scl l p 3 scl sync h t n scl 3 scl c scl n a 3 a scl sync h t sync ot ts e 3 scl n c o scl n c cln cal sy cln convst sy c s cal sc t c cln cal 3 ac p s s c t c cln cal 3 s o c t c cln elay cl scl notes s c a v v s t 3 3 scl hz scl cln t convst convst p v v scl scl cln t v t t t v t t n o n t hz s tn speccatons av v v cln hz t a t n t a
ad7851 e6e rev. b typical timing diagrams figures 2 and 3 show typical read and write timing diagrams. figure 2 shows the reading and writing after conversion in interface modes 2 and 3. to attain the maximum sample rate of 285 khz in interface modes 2 and 3, reading and writing must be performed during conversion. figure 3 shows the timing dia- gram for interface modes 4 and 5 with sample rate of 285 khz. at least a 330 ns acquisition time must be allowed (the time from the falling edge of busy to the next rising edge of convst convst a v a c l to otpt pn ol oh l c o t s polaty pn loc hh sync p scl p 3 sy op convst p ot op n p theestate theestate convet convet 3 a n 3 a 3 n t t o 3 polaty pn loc hh sync ( o/p) sclk (o/p) t 4 busy (o/p) convst (i/p) t 2 t 5 t 11 t 12 t 9 t 10 15 6 16 dout (o/p) db0 db11 t 8 din (i/p) db15 db0 three-state db11 three-state db15 t convert t convert = 3.25s max, t 1 = 100ns min, t 5 = 30ns max, t 7 = 30ns min t 1 t 6 t 7 figure 3. timing diagram (typical read and write operation for interface modes 4, 5)
e7e rev. b ad7851 absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v analog input voltage to agnd . . . . . e0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . e0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . e0.3 v to dv dd + 0.3 v ref in /ref out to agnd . . . . . . . . . . e0.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . . 10 ma operating temperature range commercial (a, k versions) . . . . . . . . . . . e40 c to +125 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c pdip package, power dissipation . . . . . . . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 105 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . 34.7 c/w lead temperature, (soldering, 10 secs) . . . . . . . . . . 260 c soic, ssop package, power dissipation . . . . . . . . . 450 mw ja thermal impedance . . 75 c/w (soic), 122.28 c/w (ssop) jc thermal impedance . . . 25 c/w (soic), 31.25 c/w (ssop) pinout for dip, soic, and ssop 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ad7851 top view (not to scale) convst busy sleep ref in /ref out av dd agnd c ref 1 c ref 2 ain(+) ain(e) nc agnd sync sclk clkin din dout dgnd dv dd cal sm2 sm1 polarity amode nc = no connect ordering guide 1 linearity temperature error throughput throughput package model range (lsb) 2 rate (ksps) at 125 c (ksps) description options 3 ad7851an e40 c to +85 c 2 333 238 pdip n-24 ad7851kn 0 c to 85 c 1 285 238 pdip n-24 ad7851ar e40 c to +85 c 2 333 238 soic r-24 ad7851ar-reel e40 c to +85 c 2 333 238 soic r-24 ad7851arz 3 e40 c to +85 c 2 333 238 soic r-24 ad7851arz-reel 3 e40 c to +85 c 2 333 238 soic r-24 ad7851kr 0 c to 85 c 1 285 238 soic r-24 AD7851KR-REEL 0 c to 85 c 1 285 238 soic r-24 ad7851krz 3 0 c to 85 c 1 285 238 soic r-24 ad7851krz-reel 3 0 c to 85 c 1 285 238 soic r-24 ad7851ars e40 c to +85 c 2 333 238 ssop rs-24 ad7851ars-reel e40 c to +85 c 2 333 238 ssop rs-24 eval-ad7851cb 4 evaluation board eval-control brd2 5 controller board notes 1 both a and k grades are guaranteed up to 125 c, but at a lower throughput of 238 khz (5 mhz). 2 linearity error refers to the integral linearity error. 3 z = pb-free part. 4 this can be used as a standalone evaluation board or in conjunction with the eval-control board for evaluation/demonstration pu rposes. 5 this board is a complete unit allowing a pc to control and communicate with all analog devices, inc. evaluation boards ending i n the cb designators. to order a complete evaluation kit, the particular adc evaluation board needs to be ordered, e.g., eval-ad7851cb, the eval-control brd2, a nd a 12 v ac trans- former. see the evaluation board application note for more information. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7851 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. lead temperature, soldering vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up.
ad7851 e8e rev. b terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. total unadjusted error this is the deviation of the actual code from the ideal code tak- ing all errors into account (gain, offset, integral nonlinearity, and other errors) at any point along the transfer function. unipolar offset error this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal ain(+) voltage (ain(e) + 1/2 lsb) when operating in unipolar mode. positive full-scale error this applies to unipolar and bipolar modes and is the deviation of the last code transition from the ideal ain(+) voltage (ain(e) + full scale e 1.5 lsb) after the offset error has been adjusted out. negative full-scale error this applies to bipolar mode only and is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal ain(+) voltage (ain(e) e v ref /2 + 0.5 lsb). bipolar zero error this is the deviation of the midscale transition (all 1s to all 0s) from the ideal ain(+) voltage (ain(e) e 1/2 lsb). track-and-hold acquisition time the track-and-hold amplifier returns into track mode at the end of conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal-to-(noise + distortion) ratio this is the measured ratio of signal-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza- tion process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal-to-(noise + distortion) = ( 6.02 n + 1.76 )db thus, for a 14-bit converter, this is 86 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7851, it is defined as thd vvvvv v (d ) 20 log b = ++++ () 2 2 3 2 4 2 5 2 6 2 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second-order terms include (fa + fb) and (fa e fb), while the third-order terms include (2fa + fb), (2fa e fb), (fa + 2fb), and (fa e 2fb). testing is performed using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. power supply rejection ratio (psrr) psrr is defined as the ratio of the power in adc output at fre- quency f to the power of the full-scale sine wave applied to the supply voltage (v dd ). the units are in lsb, % of fs per % of supply voltage, or expressed logarithmically, in db (psrr (db) = 10 log (pf/pfs)). full power bandwidth (fpbw) fpbw is that frequency at which the amplitude of the recon- structed fundamental (using ffts and neglecting harmonics and snr) is reduced by 3 db for a full-scale input.
e9e rev. b ad7851 pin function descriptions pin no. mnemonic description 1 convst c s l a v sy o t convst cal sy a 3 sleep s l p a l c a l s p e n o t e ot t v t av av v c e av av a p s v v an a ac c e c t ac t an c e c t t an an a p c an av an an a n c an av nc n c p 3 aoe a p t a l v e an an v e an an an an a l v e v e an an v e v e an an an v e an v v e v polaty s c p t scl t scl a l scl l scl t scl s s s p t s t s s s p t s t cal c t a a l t n t v s v v n ot s o t n s t t t cln c s hz hz s 3 scl s p c l t scl s s t scl polaty sync t s s t ) .
ad7851 e10e rev. b ad7851 on-chip registers the ad7851 powers up with a set of default conditions, and the user need not ever write to the device. in this case, the ad7851 w ill operate as a read-only adc. the ad7851 still retains the flexibility for performing a full power-down and a full self-calibrati on. note that the din pin should be tied to dgnd for operating the ad7851 as a read-only adc. extra features and flexibility, such as performing different power-down options, different types of calibrations, including sys tem cali- bration, and software conversion starts can be selected by writing to the part. the ad7851 contains a control register , adc output data register , status register , test register, and 10 calibration registers . the control register is write-only, the adc output data register and the status register are read-only, and the test and calibr ation registers are both read/write registers. the test register is used for testing the part and should not be written to. addressing the on-chip registers writing a write operation to the ad7851 consists of 16 bits. the two msbs, addr0 and addr1, are decoded to determine which regis- ter is addressed, and the subsequent 14 bits of data are written to the addressed register. it is not until all 16 bits are wri tten that the data is latched into the addressed register. table i shows the decoding of the address bits, while figure 4 shows the overa ll write register hierarchy. table i. write register addressing addr1 addr0 comment 00 this combination does not address any register so the subsequent 14 data bits are ignored. 01 this combination addresses the test register . the subsequent 14 data bits are written to the test register. 10 this combination addresses the calibration registers . the subsequent 14 data bits are written to the selected calibration register. 11 this combination addresses the control register . the subsequent 14 data bits are written to the control register. reading to read from the various registers the user must first write to bits 6 and 7 in the control register, rdslt0 and rdslt1. these bits are decoded to determine which register is addressed during a read operation. table ii shows the decoding of the read addr ess bits while figure 5 shows the overall read register hierarchy. the power-up status of these bits is 00 so that the default read will be from the adc output data register. once the read selection bits are set in the control register, all subsequent read operations that follow will be from the selec ted register until the read selection bits are changed in the control register. table ii. read register addressing rdslt1 rdslt0 comment 00 all successive read operations will be from adc output data register . this is the power-up default setting. there will always be two leading zeros when reading from the adc output data register. 01a ll successive read operations will be from test register . 10a ll successive read operations will be from calibration registers . 11a ll successive read operations will be from status register . addr1, addr0 decode test register control register gain (1) offset (1) dac (8) gain (1) offset (1) offset (1) gain (1) 01 10 11 00 01 10 11 calslt1, calslt0 decode calibration registers figure 4. write register hierarchy/address decoding rdslt1, rdslt0 decode test register calibration registers status register gain (1) offset (1) dac (8) gain (1) offset (1) offset (1) gain (1) 01 10 11 00 01 10 11 calslt1, calslt0 decode adc output data register 00 figure 5. read register hierarchy/address decoding
e11e rev. b ad7851 control register the arrangement of the control register is shown below. the control register is a write-only register and contains 14 bits of d ata. the control register is selected by putting two 1s in addr1 and addr0. the function of the bits in the control register are describ ed below. the power-up status of all bits is 0. msb zero zero zero zero pmgt1 pmgt0 rdslt1 rdslt0 2/ 3 oe convst cl clslt clslt stcl ls c n c 3 eo t eo eo eo p t pt sleep p t p slt t s t slt 3 oe s n t convst c s a l t c 3 cal c a t calslt c s s c t calslt stcal calslt calslt stcal t t stcal stcal calslt calslt c t c s cal calslt calslt c t a ac t h t t a ac h t t
ad7851 e12e rev. b status register the arrangement of the status register is shown below. the status register is a read-only register and contains 16 bits of data . the status register is selected by first writing to the control register and putting two 1s in rdslt1 and rdslt0. the function of t he bits in the status register is described below. the power-up status of all bits is 0. write to control register setting rdslt0 = rdslt1 = 1 read status register start figure 6. flowchart for reading the status register msb zero busy zero zero zero zero pmgt1 pmgt0 rdslt1 rdslt0 2/ 3 oe cl clslt clslt stcl ls s n c eo t s cc 3 eo t eo eo eo p t pt sleep p t s t v p o slt s t slt 3 oe s t 3 cal c a t calslt c s s c t stcal calslt t calslt calslt stcal c
e13e rev. b ad7851 calibration registers the ad7851 has 10 calibration registers in all, 8 for the dac, 1 for the offset, and 1 for gain. data can be written to or read from all 10 calibration registers. in self- and system calibration, the part automatically modifies the calibration registers; only if t he user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. addressing the calibration registers the calibration selection bits in the control register, calslt1 and calslt0, determine which of the calibration registers are addressed (see table iv). the addressing applies to both the read and write operations for the calibration registers. the user should not attempt to read from and write to the calibration registers at the same time. table iv. calibration register addressing calslt1 calslt0 this combination addresses the 0 0 gain (1) , offset (1) and dac registers (8) . ten registers in total. 0 1 gain (1) and offset (1) registers. two registers in total. 1 0 offset register . one register in total. 1 1 gain register . one register in total. writing to/reading from the calibration registers for writing to the calibration registers, a write to the control reg- ister is required to set the calslt0 and calslt1 bits. for reading from the calibration registers, a write to the control regis- ter is required to set the calslt0 and calslt1 bits, but also to set the rdslt1 and rdslt0 bits to 10 (this addresses the calibration registers for reading). the calibration register pointer is reset on writing to the control register setting the calslt1 and calslt0 bits, or upon completion of all the calibration register write/read operations. when reset, it points to the first calibration register in the selected write/read sequence. the cali- bration register pointer will point to the gain calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own (calslt1 = 1, calslt0 = 0). where more than one calibration register is being accessed, the calibration register pointer will be automatically incremented after each calibration register write/read operation. the order in which the 10 calibration registers are arranged is shown in figure 7. the user may abort at any time before all the calibration register write/read operations are completed, and the next control register write operation will reset the cali- bration register pointer. the flowchart in figure 8 shows the sequence for writing to the calibration registers and figure 9 shows the sequence for reading. cal register address pointer calibration registers gain register offset register dac 1st msb register dac 8th msb register (1) (2) (3) (10) calibration register address pointer position is determined by the number of calibration registers addressed and the number of read/write operations. figure 7. calibration register arrangement when reading from the calibration registers there will always be two leading zeros for each of the registers. when operating in serial interface mode 1, the read operations to the calibration registers cannot be aborted. the full number of read operations must be completed (see the serial interface summary section for more detail). start write to cal register ( addr1 = 1, addr0 = 0) finished last register write operation or abort ? yes no cal register pointer is automatically reset write to control register setting stcal = 0 and calslt1, calslt0 = 00, 01, 10, 11 cal register pointer is automatically incremented figure 8. flowchart for writing to the calibration registers
ad7851 e14e rev. b finished last register write operation or abort ? yes no cal register pointer is automatically incremented read cal register cal register pointer is automatically reset write to control register setting stcal = 0, rdslt1 = 1, rdslt0 = 0, and calslt1, calslt0 = 00, 01, 10, 11 start figure 9. flowchart for reading from the calibration registers adjusting the offset calibration register the offset calibration register contains 16 bits, 2 leading 0s, and 14 data bits. by changing the contents of the offset register, dif- ferent amounts of offset on the analog input signal can be com- pensated for. increasing the number in the offset calibration register compensates for the negative offset on the analog input signal, and decreasing the number in the offset calibration regis- ter compensates for the positive offset on the analog input signal. the default value of the offset calibration register is approxi- mately 0010 0000 0000 0000. this is not an exact value, but the value in the offset register should be close to this value. each of the 14 data bits in the offset register is binary weighted; the msb has a weighting of 5% of the reference voltage, the msb-1 has a weighting of 2.5%, the msb-2 has a weighting of 1.25%, and so on down to the lsb which has a weighting of 0.0006%. this gives a resolution of 0.0006% of v ref approximately. more accurately the resolution is (0.05 v ref )/2 13 v = 0.015 mv, w ith a 2.5 v reference. the maximum offset that can be compensated for is 5% of the reference voltage, which equates to 125 mv with a 2.5 v reference and 250 mv with a 5 v reference. q. if a +20 mv offset is present in the analog input signal and the reference voltage is 2.5 v, what code needs to be written to the offset register to compensate for the offset? a. the 2.5 v reference implies that the resolution in the off- set register is 5% 2.5 v/2 13 = 0.015 mv. 20 mv/ 0.015 mv = 1310.72; rounding to the nearest number gives 1311. in binary terms this is 0101 0001 1111, therefore decrease the offset register by 0101 0001 1111. this method of compensating for offset in the analog input signal allows for fine-tuning the offset compensation. if the offset on the analog input signal is known, there will be no need to apply the offset voltage to the analog input pins to do a system calibration. the offset compensation can take place in software. adjusting the gain calibration register the gain calibration register contains 16 bits, 2 leading 0s, and 14 data bits. the data bits are binary weighted as in the offset calibration register. the gain register value is effectively multi- plied by the analog input to scale the conversion result over the full range. increasing the gain register compensates for a smaller analog input range and decreasing the gain register compensates for a larger input range. the maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage.
e15e rev. b ad7851 circuit information the ad7851 is a fast, 14-bit single-supply adc. the part requires an external 6/7 mhz master clock (clkin), two c ref capacitors, a convst t ac t ac a ac t a v v v t a a convst a a cal an a c po t ssop convete etals t cln c a convst convst o convst t cln convst convst cln t cln cln cln t av v an an aoe c e c e sleep n ot sync s s convst an n cln scl e n e ot polaty a analo v spply v npola ane seal oe selecton ts aste cloc npt conveson stat npt ae sync otpt seal ata otpt cal ato cal on poep ntenal etenal eeence v to v e npt hzhz oscllato seal cloc otpt v 333hzhz plse eneato optonal etenal eeence ae analo v spply n at n no tn to evce ch ch ch3 ch osclloscope lean eos o ac ata t c 3 hz hz a a cln cln hz hz sy t convst h t a 333 hz a cln cln 3 hz cln hz 3 3 hz cln hz a typcal connecton aa a t n n t an n t cal t scl sync s s v t z s n av v sleep n s p o
ad7851 e16e rev. b analog input the equivalent circuit of the analog input section is shown in figure 11. during the acquisition interval, the switches are both in the track position and the ain(+) charges the 20 pf capacitor through the 125 resistance. on the rising edge of convst s s s an t an n a t ac n a t ac t an ac ac t an an an capacto ac copaato hol tac s noe a s tac hol an an c e a e c a t t sy t t t acq = 9 (r in + 125 ) 20 pf where r in is the source impedance of the input signal, and 125 , 20 pf is the input r, c. dc/ac applications for dc applications, high source impedances are acceptable, provided there is enough acquisition time between conversions to charge the 20 pf capacitor. the acquisition time can be cal- culated from the above formula for different source impedances. for example, with r in = 5 k , the required acquisition time will be 922 ns. for ac applications, removing high frequency components from the analog input signal is recommended by use of an rc low-pass filter on the ain(+) pin, as shown in figure 13. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp will be a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases, and the performance will degrade. figure 12 shows a graph of the total harmonic distor- tion versus the analog input signal frequency for different source impedances. with the setup as in figure 13, the thd is at the e90 db level. with a source impedance of 1 k and no capacitor on the ain(+) pin, the thd increases with frequency. thd (db) input frequency ( khz ) e50 e60 e110 e100 e80 e90 e70 1 166 10 20 50 80 thd vs. frequency for different source impedances r in = 560 r in = 10 , 10nf as in figure 13 140 120 100 figure 12. thd vs. analog input frequency in a single-supply application (5 v), the v+ and ve of the op amp can be taken directly from the supplies to the ad7851 which elimi- nates the need for extra external power supplies. w hen operating with rail-to-rail inputs and outputs at frequencies greater than 10 kh z, care must be taken in selecting the particular op amp for the application. in particular, for single-supply applications the input amplifiers should be connected in a gain of e1 arrangement to get the optimum performance. figure 13 shows the arrangement for a single-supply application with a 10 and 10 nf low-pass fil- ter (cutoff frequency 320 khz) on the ain(+) pin. note that the 10 nf is a capacitor with good linearity to ensure good ac performance. recommended single-supply op amp is the ad820. ic1 5v 10k 10k 10k v+ ve 10k 10 ad820 v in ev ref /2 to +v ref /2 v ref /2 10 f 0.1 f 10nf (npo) to ain(+) of ad7851 figure 13. analog input buffering
e17e rev. b ad7851 transfer functions for the unipolar range, the designed code transitions occur mid- way between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fs e3/2 lsbs). the output coding is straight binary for the unipolar range with 1 lsb = fs/16384 = 4.096 v/16384 = 0.25 mv when v ref = 4.096 v. the ideal input/output transfer characteristic for the unipolar range is shown in figure 16. +fs e 1lsb output code 0v 111...111 111...110 111...101 111...100 000...011 000...001 000...000 000...010 v in = (ain(+) e ain(e)), input voltage 1lsb 1lsb = fs 16384 figure 16. ad7851 unipolar transfer characteristic figure 15 shows the ad7851?s v ref /2 bipolar analog input con- figuration (where ain(+) cannot go below 0 v, so for the full bipo- lar range the ain(e) pin should be biased to +v ref /2). once again the designed code transitions occur midway between successive integer lsb values. the output coding is twos complement with 1 lsb = 16384 = 4.096 v/16384 = 0.25 mv . the ideal input/ output transfer characteristic is shown in figure 17. fs = v ref v 1lsb = fs 16384 output code v ref /2 011...111 011...110 000...001 000...000 100...001 100...000 100...010 v in = (ain(+) e ain(e)), input voltage 0v + fs e 1 lsb 111...111 (v ref /2) e 1 lsb (v ref /2) + 1 lsb figure 17. ad7851 bipolar transfer characteristic input ranges the analog input range for the ad7851 is 0 v to v ref in both the unipolar and bipolar ranges. the only difference between the unipolar range and the bipolar range is that in the bipolar range the ain(e) has to be biased up to +v ref /2 and the output coding is twos complement (see table v and figures 14 and 15). the unipolar or bipolar mode is selected by the amode pin (0 for the unipolar range and 1 for the bipolar range). table v. analog input connections analog input input connections connection range ain(+) ain(e) diagram amode 0 v to v ref 1 v in agnd figure 8 dgnd v ref /2 2 v in v ref /2 figure 9 dv dd notes 1 output code format is straight binary. 2 range is v ref /2 biased about v ref /2. output code format is twos complement. note that the ain(e) pin on the ad7851 can be biased up above agnd in the unipolar mode also, if required. the advantage of biasing the lower end of the analog input range away from agnd is that the user does not have to have the analog input swing all the way down to agnd. this has the advantage in true single-supply applications that the input amplifier does not have to swing all the way down to agnd. the upper end of the analog input range is shifted up by the same amount. care must be taken so that the bias applied does not shift the upper end of the analog input above the av dd supply. in the case where the reference is the supply, av dd , the ain(e) must be tied to agnd in unipolar mode. ain(+) ain(e) amode ad7851 unipolar analog input range selected dout straight binary format v in = 0 to v ref track and hold amplifier figure 14. 0 v to v ref unipolar input configuration twos complement format v ref /2 dv dd ain(+) ain(e) amode ad7851 unipolar analog input range selected dout v in = 0 to v ref track and hold amplifier figure 15. v ref /2 about v ref /2 bipolar input configuration
ad7851 e18e rev. b reference section for specified performance, it is recommended that when using an external reference this reference should be between 4 v and the analog supply av dd . the connections for the relevant refer- ence pins are shown in the typical connection diagrams. if the internal reference is being used, the ref in /ref out pin should have a 100 nf capacitor connected to agnd very close to the ref in /ref out pin. these connections are shown in figure 18. if the internal reference is required for use external to the adc, it should be buffered at the ref in /ref out pin and a 100 nf capacitor connected from this pin to agnd. the typical noise performance for the internal reference with 5 v supplies is 150 nv/ hz hz v e n e ot a analo spply v av v c e c e c t e n e ot t e n e ot t av av e n e ot an e n e ot c e av t av av t av e n e ot a analo spply v av v c e c e c av a peoance cves t a 333 hz hz eency hz sn av v v saple 333hz n hz sn th t p sn v v npt eency hz sn ato sn t ac psrr ( db ) = 10 log (pf/pfs) pf is the power at frequency f in adc output, pfs is the power of a full-scale sine wave. here a 100 mv peak-to-peak sine wave is coupled onto the av dd supply while the digital supply is left unaltered.
e19e rev. b ad7851 input frequency (khz) e72 e74 e90 0.91 100 13.4 25.7 38.3 50.3 e76 e78 e80 e88 psrr (db) e82 e84 e86 63.5 74.8 87.4 av dd = dv dd = 5.0v 100mv pk-pk sinewave on av dd ref in = 4.098 ext reference figure 22. psrr vs. frequency power-down options the ad7851 provides flexible power management to allow the user to achieve the best power performance for a given throughput rate. the power management options are selected by programming the power management bits, pmgt1 and pmgt0, in the con- trol register and by use of the sleep t v z t a a a t t p t a a s oc sleep pt pt sleep t sps a sleep sleep pt pt t v a t v p o pt pt sleep p c s s s s p s ss vtov e npt ntn notn toevce 3eoe selecte centtp v v n n oe c e c e sleep n ot snc s s convst n n cln scl e n e ot polt nlo v v npolne seloe selectonts ste cloc npt conveson sttnpt seltotpt cl ntenl eeence oscllto selclocotpt 333plse eneto optonl etenl eeence toclon poep e topoe onte conveson lopoe c p 3 tlpc
ad7851 e20e rev. b power-up times using an external reference when the ad7851 is powered up, the part is powered up from one of two conditions: first, when the power supplies are initially powered up and; secondly, when the parts are powered up from either a hardware or software power-down (see previous section). when av dd and dv dd are powered up, the ad7851 enters a mode whereby the convst t 3 a c po sleep sleep t convst a t a 3 t a t sps sps a convst t sleep pt pt a sy t convst a a t convst convst t 3 convet poep te noal opeaton ll poeon poep te stat conveson on sn ee poe p on alln ee convst sy convst c oc v v n ot t t up = 9 r c where r 150k and c = external capacitor. the recommended value of the external capacitor is 100 nf; this gives a power-up time of approximately 135 ms before a calibration is initiated and normal operation should commence. when c ref is fully charged, the power-up time from a hardware or software power-down reduces to 5 s. this is because an internal switch opens to provide a high impedance discharge path for the reference capacitor during power-down?see figure 25. an added advantage of the low charge leakage from the reference capacitor during power-down is that even though the reference is being pow- ered down between conversions, the reference capacitor holds the reference voltage to within 0.5 lsbs with throughput rates of 100 samples/second and over with a full power-down between conver- sions. a high input impedance op amp, such as the ad707, should be used to buffer this reference capacitor if it is being used exter- nally. note, if the ad7851 is left in its powered-down state for more than 100 ms, the charge on c ref will start to leak away and the power-up time will increase. if this long power-up time is a problem, the user can use a partial power-down for the last conver- sion so the reference remains powered up. ad7851 ref in /ref out external capacitor switch opens during power-down buf on-chip reference to other circuitry figure 25. on-chip reference during power-down power vs. throughput rate the main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part at lower throughput rates. when using this mode of operation, the ad7851 is only powered up for the duration of the conver- sion. if the power-up time of the ad7851 is taken to be 5 s and it is assumed that the current during power up is 12 ma typ, then power consumption as a function of throughput can easily be calculated. the ad7851 has a conversion time of 3.25 s with a 6 mhz external clock. this means the ad7851 consumes 12 ma typ for 8.25 s in every conversion cycle if the parts are powered down at the end of a conversion. the graph in figure 26 shows the power consumption of the ad7851 as a function of through put. table vii lists the power consump- tion for various throughput rates.
e21e rev. b ad7851 table vii. power consumption vs. throughput throughput rate power ad7851 1 ksps 9 mw 2 ksps 18 mw throughput rate ( hz ) 100 10 0.01 0 2000 200 1 400 600 800 1000 1200 1400 1600 1800 0.1 power (mw) figure 26. power vs. throughput ad7851 note when setting the power-down mode by writing to the part, operating in an interface mode other than interface modes 4 and 5 is recommended. this way the user has more control to initiate power-down and power-up commands. calibration section calibration overview the automatic calibration that is performed on power-up ensures that the calibration options covered in this section will not be required for a significant number of applications. the user will not have to initiate a calibration unless the operating conditions change (clkin frequency, analog input mode, reference voltage, temperature, and supply voltages). the ad7851 has a number of calibration features that may be required in some applications, and there are a number of advantages in performing these differ- ent types of calibration. first, the internal errors in the adc can be reduced significantly to give superior dc performance; and second, system offset and gain errors can be removed. this allows the user to remove reference errors (whether internal or external references) and to make use of the full dynamic range of the ad7851 by adjusting the analog input range of the part for a specific system. the ad7851 has two main calibration modes: self-calibration and system calibration. there are various options in both self- calibration and system calibration as outlined previously in table iii. all the calibration functions can be initiated by puls- ing the cal stcal t cal t t v a hz hz t t v c t a hz cln t s s c t o o 3 3 a c po t cal a a cal n t cal z t h z cal o cal 3 hz cln t a t sc t t ac o ac t ac ac a ac z
ad7851 e22e rev. b system offset calibration sys offset v ref e 1lsb agnd max system offset is 5% of v ref max system full scale is 2.5% from v ref analog input range v ref e 1lsb analog input range sys offset agnd max system offset is 5% of v ref v ref + sys offset figure 28. system offset calibration figure 29 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog input range has been increased after the system gain calibration is completed. a system full-scale voltage less than the reference voltage may also be accounted for a by a system gain calibration. system gain calibration v ref e 1lsb agnd max system full scale is 2.5% from v ref analog input range v ref e 1lsb analog input range agnd sys full s. sys full s. max system full scale is 2.5% from v ref figure 29. system gain calibration finally in figure 30 both the system offset and gain are accounted for by the system offset followed by a system gain calibration. first the analog input range is shifted upwards by the positive system offset and then the analog input range is adjusted at the top end to account for the system full scale. system offset calibration followed by system gain calibration sys offset v ref e 1lsb agnd max system offset is 5% of v ref max system full scale is 2.5% from v ref analog input range v ref e 1lsb analog input range sys offset agnd max system offset is 5% of v ref v ref + sys offset sys f.s. max system full scale is 2.5% from v ref sys f.s. figure 30. system (gain + offset) calibration self-calibration timing figure 27 shows the timing for a full self-calibration. here the busy line stays high for the full length of the self-calibration. a self-calibration is initiated by bringing the cal stcal cal pulse width must take account of the power-up time). the busy line is triggered high from the rising edge of cal sy cal n cln a cal cln cal p sy op cal t sc sy cal t sy t t v t s c s a a t v e v e t an an v e an v e an v e an an an v e v e an v e v e an v e v e an 3 a
e23e rev. b ad7851 system gain and offset interaction the inherent architecture of the ad7851 leads to an interaction between the system offset and gain errors when a system calibra- tion is performed. therefore, it is recommended to perform the cycle of a system offset calibration followed by a system gain cali- bration twice. separate system offset and system gain calibrations reduce the offset and gain errors to at least the 14-bit level. by performing a system offset calibration first and a system gain calibration second, priority is given to reducing the gain error to zero before reducing the offset error to zero. if the system errors are small, a system offset calibration would be performed, fol- lowed by a system gain calibration. if the systems errors are large (close to the specified limits of the calibration range), this cycle would be repeated twice to ensure that the offset and gain errors were reduced to at least the 14-bit level. the advantage of doing separate system offset and system gain calibrations is that the user has more control over when the analog inputs need to be at the required levels, and the convst a t t z s c t t 3 cal note that if the part is in power- down mode the cal pulse width must take account of the power-up time) . if a full system calibration is performed in the software, it is easier to perform separate gain and offset calibrations so that the convst t cal ac sy convst t t sy ac n an setp convst sy t convst sy t sy cal t 3 cal cal ac t sy convst p an p setp cal p sy op cal cal v syste ll scale v oset n a cln a cal cln a cal cln 3 t s c t 3 h cal cal t cal sy t setp cal sy an p setp cal p sy op cal v syste ll scale o v syste oset 3 t s s o c
ad7851 e24e rev. b serial interface summary table ix details the five interface modes and the serial clock edges from which the data is clocked out by the ad7851 (dout edge) and that the data is latched in on (din edge). the logic level of the polarity pin is shown and it is clear that this reverses the edges. in interface modes 4 and 5 the sync scl 3 sync scl polaty t sync s s scl t sync s polaty sync s sync polaty sync s sync t scl a e polaty ot n p e e 3 scl scl s cl scl scl scl s cl scl s n t sync sync t sync t n sync csp t z a p c t p s s n s s c e scl sync sync 3 a scl sync s p c sp a t c p sp t a c p sp a t s s p p p c c l n pcc o p hc 3 spsp l hc 3 sp pcc e s asp c scl sp e s sp sync a sp spl ts3c3 hc sp s a n c s c scl s sync asp sp s sp a sp c s sp c scl spl s sync ts3c ts3c ts3c3 ts3c ts3lc
e25e rev. b ad7851 db15 db0 db0 db15 t 3 din (i/o) t 3 t 11 t 6 116 16 1 t 5a t 12 din becomes an input three-state t 6 t 11 din becomes an output t 3 = e0.4 t sclk min (noncontinuous sclk) 0.4 t sclk min/max (continuous sclk), t 6 = 45 max, t 7 = 30ns min, t 8 = 20 min polarity pin logic high sync (i/p) sclk (i/p) t 8 t 14 t 7 da ta write data read figure 33. timing diagram for read/write operation with din as an input/output (interface mode 1, sm1 = sm2 = 0) db15 db0 db0 db15 din (i/o) t 6 = 45 max, t 7 = 30ns min, t 8 = 20 min, t 13 = 90 max, t 14 = 50ns max 6 116 16 1 t 13 t 6 din becomes an input t 6 polarity pin logic high sclk (i/p) t 8 t 14 t 7 data write data read figure 34. timing diagram for read/write operation with din as an input/output and sync t ss ttnscton tn convst 3 oe t convst convst 33 3 h n t sync 33 3 33 scl a scl n sync n t sync n scl o n n scl 33 sync t polaty scl 3 sync sync n t scl n h scl t n n
ad7851 e26e rev. b mode 2 (3-wire spi/qspi interface mode) default interface mode figure 35 shows the timing diagram for interface mode 2 which is the spi/qspi interface mode. here the sync sync scl sync scl sync scl 3 sync ot t scl sync z ot t ot sync n scl scl t polaty scl sync theestate theestate 3 3 3 cln n noncontnos scl scl na contnos scl a 3 n n 3 n noncontnos scl 3 scl na contnos scl polaty pn loc hh sync p 3 scl p 3 ot op n p 3 spsp t o n ot o sync ss cn nnoncontnossc sc ncontnossc n n n tstt tstt otyn oc sync sc oto n sto sync tss s s sync sync scl sync t scl t sync ot t sync ot scl o sync ot t scl t polaty scl sync
e27e rev. b ad7851 mode 4 and 5 (self-clocking modes) the timing diagrams in figure 38 and figure 39 are for inter- face modes 4 and 5. interface mode 4 has a noncontinuous sclk output and interface mode 5 has a continuous sclk output (sclk is switched off internally during calibration for both modes 4 and 5). these modes of operation are especially different from all the other modes because the sclk and sync t sync scl t cln scl scl cln sync scl t t 3 3 3 3 te n ea n 3 te n ea n te n3 ea n the conveson eslt e to te n s ea hee 3 3 conveson n conveson n conveson n 3 3 sy sync scl a convst c convst t convst sy t convst sync cln 3 cln scl ot t n a scl t 3 convst hz cln a sync sy t convst 33 sy 3 t 3 t hz convst p scl op conveson ens 3 late seal ea an te opeatons otpt seal sht este s eset ea opeaton shol en po to net sn n sy op sync op conveson s ntate an tacanhol oes nto hol ee o convst n convet 3 3 t s s sp 3 3 t a sync c scl 3 o scl t sync t scl ot t n scl t polaty scl t sync scl scl 3 t n ot 3 3 theestate theestate polaty pn loc hh sync op 3 scl op a ot op n p scl noncontnos scl a 3 n n a a c 3 t sync oscoc nss
ad7851 e28e rev. b if the user has control of the convst s convst convst t sync h convst t convst sync sync t sync convst convst t convst seal nteace oe poe on apply cln snal at o atoatc calaton n connecte to n no yes stat at o sy snal to o lo plse convst pn ea ata n conveson at appoately ate convst sn ee apply sync ee scl an ea conveson eslt on ot pn plse convst pn sync atoatcally oes lo ate convst sn ee scl atoatcally actve ea conveson eslt on ot pn 3 s a conn the a a o ac t a a ac h cln cln t a hz cl
e29e rev. b ad7851 serial interface mode ? no yes transfer data during conversion ? apply sync (if required), sclk, read current conversion result on dout pin, and write all 0s on din pin wait for busy signal to go low or wait for busy bit = 0 apply sync (if required), sclk, write to control register setting convst bit to 1, read current conversion result on dout pin 2, 3 initiate conversion in software ? wait approximately 200ns after convst rising edge apply sync (if required), sclk, read previous conversion result on dout pin, and write all 0s on din pin no yes transfer data during conversion apply sync (if required), sclk, write to control register setting convst bit to 1, read previous conversion result on dout pin (see note) yes no note: when using the software conversion start and transferring data during conversion, the user must ensure the control register write operation extends beyond the falling edge of busy. the falling edge of busy resets the convst bit to 0 and only after this time can it be reprogrammed to 1 to start the next conversion. start power on, apply clkin signal, wait for automatic calibration pulse convst pin wait for busy signal to go low or wait for busy bit = 0 figure 41. flowchart for setting up, reading, and writing in interface modes 2 and 3 writing to the ad7851 for accessing the on-chip registers, it is necessary to write to the part. to enable serial interface mode 1, the user must also write to the part. figures 41, 42, and 43 shows how to configure the ad7851 for each of the different serial interface modes. the continuous loops on all diagrams indicate the sequence for more than one conversion. the options of using a hardware (pulsing the convst convst convst v sy l sy 3 c 3
ad7851 e30e rev. b interface mode 1 configuration figure 42 shows the flowchart for configuring the part in inter- face mode 1. this mode of operation can only be enabled by writing to the control register and setting the 2/ 3 oe n seal nteace oe poe on apply cln snal at o atoatc calaton no yes at o sy snal to o lo o at o sy t ea ata n conveson apply sync ee scl ea cent conveson eslt on n pn ntate conveson n sotae at appoatly ate convst sn ee o ate en o contol este te apply sync ee scl ea pevos conveson eslt on n pn no yes apply sync ee scl te to contol este settn the e oe an convst t to stat apply sync ee scl te to contol este settn the e oe plse convst pn s c 3 a t poe on apply cln snal at o atoatc calaton sync atoatcally oes lo ate convst sn ee plse convst pn scl atoatcally actve ea cent conveson eslt on ot pn te to contol este on n pn stat seal nteace oe 3 s
e31e rev. b ad7851 (8xc51 /l51) /pic 17c42 p3.0/dt p3.1/ck ad7851 convst clkin sclk din sync sm1 sm2 polarity o ptional 7mhz/6mhz busy ( int0 /p3.2)/int dgnd for 8xc51/l51 dv dd for pic17c42 master slave o ptional figure 45. 8xc51/pic17c42 interface ad7851 to 68hc11/16/l11/pic16c42 interface figure 46 shows the ad7851 spi/qspi interface to the 68hc11/16/l11/pic16c42. the sync n t c st spc sc c cpol hcl cpha t cln convst c t sy c sy n hc sp s ss sync t hc sp cp cp t n ot 3 hz cln t c a hc lpcc sc ss a convst cln scl ot sy s s polaty o ptonal hzhz sync so n at n o no tn to pat aste slave n v o ptonal os v o hc sp n o hc sp v sp hc sp hc hc copocesso nteacn t n n convst scl ot n n t scl cln 3 sync scl 3 sync scl n cln scl scl cln n ot sync convst cln scl a hz hz aste cloc sync snal to ate the scl se al ata otpt c onveson stat s n scl t cln a cpcc a cpcc v t c t scl n t sync t sy cpcc c hz hz a hz t cln a c c h scl cln c t convst t n 3 hz cln n t cpcc a
ad7851 e32e rev. b ad7851 to adsp-21xx interface figure 47 shows the ad7851 interface to the adsp-21xx. the adsp-21xx is the slave and the ad7851 is the master. the ad7851 is in interface mode 5. for the adsp-21xx, the bits in the serial port control register should be set up as tfsr = rfsr = 1 (need a frame sync for every transfer), slen = 15 (16-bit word length), tfsw = rfsw = 1 (alternate framing mode for transmit and receive operations), invrfs = invtfs = 1 (active low rfs and tfs), irfs = itfs = 0 (external rfs and tfs), and isclk = 0 (external serial clock). the clkin and convst asp t a scl sync asp t sy t asp a cln hz hz v a convst cln scl ot sy s s polaty o ptonal hzhz sync s n at n o no tn to pat slave aste o ptonal n v o ptonal t ts asp sc asp a spl a spl h sp a t a 3 t sp syn sc sc l l sl sl a c scl cln a c a sp a scl hz hz a convst cln scl ot sy s s polaty optonal hzhz sync n at n o no tn to pat slave optonal n v optonal sp l s sc sc aste st spl a ts3clc a ts3c t a ts3c cl cl s s t cl cl s s a sy a ts3c a cln hz hz a convst cln scl ot sy s s polaty o ptonal hzhz sync n at n o no tn to pat slave aste o ptonal n v o ptonal t s nt ts3c lc cl s cl ts3c
e33e rev. b ad7851 evaluating the ad7851 performance the recommended layout for the ad7851 is outlined in the evaluation board for the ad7851. the evaluation board package includes a fully assembled and tested evaluation board, documen- tation, and software for controlling the board from the pc via the eval-control board. the eval-control board can be used in conjunction with the ad7851 evaluation board, as well as many other analog devices evaluation boards ending in the cb designator, to demonstrate/evaluate the ac and dc perfor- mance of the ad7851. the software allows the user to perform ac (fast fourier trans- form) and dc (histogram of codes) tests on the ad7851. it also gives full access to all the ad7851 on-chip registers allowing for various calibration and power-down options to be programmed. ad785x family all parts are 12 bit, 200 ksps, 3.0 v to 5.5 v, except the ad7856 which is 14 bit, 285 ksps, 5 v supply. ad7853 e single-channel serial ad7854 e single-channel parallel ad7856 e eight-channel serial ad7858 e eight-channel serial ad7859 e eight-channel parallel application hints grounding and layout the analog and digital supplies to the ad7851 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the part has very good immunity to noise on the power supplies as can be seen by the psrr versus frequency graph. however, care should still be taken with regard to grounding and layout. the printed circuit board that houses the ad7851 should be designed such that the analog and digital sections are separated and confined to certain areas of the board . this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad7851 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad7851. if the ad7851 is in a system where multiple devices require agnd to dgnd connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the ad7851. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7851 to avoid noise coupling. the power supply lines to the ad7851 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum in parallel with 0.1 f ca- pacitors to agnd. all digital supplies should have a 0.1 f disc ceramic capacitor to dgnd. to achieve the best from these de- coupling components, they must be placed as close as possible to the device, ideally right up against the device. in systems where a common supply voltage is used to drive both the av dd and dv dd of the ad7851, it is recommended that the system?s av dd supply is used. in this case, there should be a 10 resistor between the av dd pin and dv dd pin. this supply should have the recommended analog supply decoupling capacitors between the av dd pin of the ad7851 and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the ad7851 and dgnd.
ad7851 e34e rev. b outline dimensions 24-lead plastic dual in-line package [pdip] (n-24) dimensions shown in inches and (millimeters) 24 1 12 13 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095ag 24-lead standard small outline package [soic] wide body (r-24) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ad 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122)
?5 rev. b ad7851 24-lead shrink small outline package [ssop] (rs-24) dimensions shown in millimeters 24 13 12 1 8.20 7.80 7.40 5.60 5.30 5.00 0.38 0.22 seating plane 0.05 min 0.65 bsc 2.00 max 1.85 1.75 1.65 0.95 0.75 0.55 0.25 0.09 8 4 0 0.10 coplanarity 8.50 8.20 7.90 compliant to jedec standards mo-150ag
c01332??/04(b) ?6 revision history location page 3/04?ata sheet changed from rev. a to rev. b. moved page index from page 33 to page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 updated terminology section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 updated pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 updated table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 updated control register section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 updated status register bit function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 updated circuit information section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 updated figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 updated typical connection diagram section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 updated figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 updated figure 18 and figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 updated figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 updated automatic calibration on power-on section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 updated mode 4 and 5 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 updated ad7851 as a read-only adc section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 updated figure 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 updated figure 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 updated figures 42 and 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 updated figure 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ad7851 rev. b

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